Bounding of Switching Activity in Logic Circuits

Electronic systems became an essential component of our lives. The demand for increased functionality is satisfied by higher integration which, however, make the design process more complex and introduces new problems. These problems must be considered in every step involved in the design of electronic systems. One of these steps is verification checking, whether what is manufactured will work properly. Among several properties that must be verified, power consumption is becoming more important than ever before. In the most commonly used CMOS technology a considerable amount of power is consumed due to switching which is described by switching activity. Switching activity in its broad sense is a measure of topological and temporal distribution of signal transitions for given operating environment of the circuit. This thesis addresses the problem of estimation of switching activity. The thesis presents algorithms, implementation, and results of a new method based on constraint resolution for finding an upper bound on switching activity in the combinational part of a synchronous sequential circuit. The obtained switching activity is the major component for computing circuit power consumption (peak power) and several reliability parameters (e.g., voltage drops in power busses, electromigration). It is a static (input-pattern independent) method. The constraint system representing the circuit is built of constraints defined by gates and the operating environment of the circuit. The variables of the constraint system are all possible waveforms abstracted into four classes and expressed as sets of transitions for each unit of discrete time. The constraints of the constraint system are derived from the gates. Each gate is translated into a projection function which constrains each of its terminals based on the values on all other terminals independently of the netlist distinction between gate inputs and outputs. The method rapidly com-